Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Semiconductor devices may develop defects during the fabrication processes. Inspection processes are performed at various steps during a semiconductor manufacturing process to detect defects on a specimen. Inspection processes are an important part of fabricating semiconductor devices such as integrated circuits, becoming even more important to successfully manufacture acceptable semiconductor devices as the dimensions of semiconductor devices decrease. For instance, detection of defects has become highly desirable as the dimensions of semiconductor devices decrease, as even relatively small defects may cause unwanted aberrations in the semiconductor devices.
Methods of defect detection include generating one or more wafer inspection recipes with one or more critical areas, the one or more critical areas based on wafer design data, SEM or high-resolution optical inspection images representing the design intent, or simulated images. These methods of defining critical areas, however, can be laborious and/or computationally intensive, thus requiring inspection expertise. Additionally, these methods of defining critical areas may results in wafer inspection recipes that are too limited in scope, potentially missing defects. Further, these methods may potentially miss defects because the one or more defects and signal noise are not separable (i.e. the defects are lost in noise). As such, it would be desirable to provide a solution for improved wafer inspection and defect classification to resolve manufacturing issues and provide improved wafer inspection capabilities.